The present invention relates generally to clock signal generation and particularly to an apparatus for generating a plurality of phased clock signals.
Phased clock signals have similar periods but differing phase relationships and are useful in synchronizing the orderly and controlled flow of data in a digital system. As data signals propagate through a network, they undergo delays that cannot be precisely predicted. By clocking data flow in a digital system, it is possible to insure that at a given time a particular data signal may be safely interpreted as having reached a valid logical level. Multiple phase clock signals have been produced by passing a master clock signal through a multiple tap delay line. However, such delay lines are expensive and cannot be implemented in integrated circuit form. Multiple clock phase generators utilizing digital delay elements have been used, but they typically do not operate at high frequencies.